This invention relates generally to computer processing, and more specifically, to operand fetching control as a function of branch confidence.
The need for increasing processor performance in the past has relied on a combination of microarchitecture improvements along with technology improvements. With a requirement to hold constant, or even reduce, the power/wattage envelope of a microprocessor, a transition is taking place from single thread performance to overall chip performance. While there are different balances across different markets, the general direction of multiple processor threads on a chip is becoming more prevalent in order to achieve an overall performance advantage to the customer. The threads may be evident as multiple cores on a chip and/or multiple threads on a core (e.g., SMT).
When placing more threads on a chip, the shared cache/memory bandwidth requirements increase at a faster rate than what is required for increasing the performance of a single thread. For increasing the number of cores, the cache/memory bandwidth requirements can be considered to increase with respect to the number of cores being added.
With the additional cache/memory bandwidth (for both shared on-chip cache and off-chip cache/memory), there becomes a need to control how fetching operations utilize the bandwidth (e.g., prioritization of operations) that is made available to them.